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general description the max1762/MAX1791 pwm step-down controllers provide high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high-voltage batteries to generate low-voltage cpu core, i/o, and chipset ram supplies in notebook computers and pdas. maxim? proprietary quick-pwm pulse-width modula- tor is a free-running constant on-time type with input feed-forward. its high operating frequency (300khz) allows small external components to be utilized in pc board area-critical applications such as subnotebook computers and smart phones. pwm operation occurs at heavy loads, and automatic switchover to pulse-skip- ping operation occurs at lighter loads. the external high-side p-channel and low-side n-channel mosfets require no bootstrap components. the max1762/ MAX1791 are simple, easy to compensate, and do not have the noise sensitivity of conventional fixed-frequen- cy current-mode pwms. these devices achieve high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode pwms. efficiency is further enhanced by their ability to drive synchronous-rectifier mosfets. the max1762/MAX1791 come in a 10-pin ?ax package and offer two fixed voltages (dual mode) for each device, 1.8v/2.5v/adj (max1762) and 3.3v/5.0v/adj (MAX1791). ________________________applications notebooks handy-terminals subnotebooks pdas digital cameras smart phones 1.8v/2.5v logic and i/o supplies features high operating frequency (300khz) no current-sense resistor accurate current limit ?% total dc error over line and during continuous conduction dual mode fixed output 1.8v/2.5v/adj (max1762) 3.3v/5.0v/adj (MAX1791) 0.5v to 5.5v output adjust range 5v to 20v input range automatic light-load pulse skipping operation free-running on-demand pwm foldback mode uvlo pfet/nfet synchronous buck 4.65v at 25ma linear regulator output 5? shutdown supply current 230? quiescent supply current 10-pin ?ax package max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks ________________________________________________________________ maxim integrated products 1 19-1923; rev 0; 1/01 ordering information part temp. range pin-package max1762 eub -40 c to +85 c 10 max MAX1791 eub -40 c to +85 c 10 max fb gnd cs dh vp dl out ref shdn v batt (5v to 20v) v out 1.8v/3.3v vl max1762 MAX1791 typical operating circuit 1 2 3 4 5 10 9 8 7 6 dh cs dl out fb ref vl max1762 MAX1791 max top view gnd shdn vp pin configuration for price, delivery, and to place orders, please contact maxim distribution at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. quick-pwm, dual mode, and foldback mode are a trade- marks of maxim integrated products.
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 2 _______________________________________________________________________________________ absolute maximum ratings vp, shdn to gnd ..................................................-0.3v to +22v vp to vl ..................................................................-0.3v to +22v out, vl to gnd .......................................................-0.3v to +6v dl, fb, ref to gnd ....................................-0.3v to (vl + 0.3v) dh to gnd....................................................-0.3v to (vp + 0.3v) cs to gnd ....................................................-2.0v to (vp + 0.3v) ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70 c) 10-pin max (derate 5.6mw/ c above +70 c) ...........444mw operating temperature .......................................-40 c to +85 c junction temperature ......................................................+150 c storage temperature.........................................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (v vp = 15v, vl enabled, c vl = 1f, c ref = 0.1f, t a = 0 to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units vp input voltage range v vp 520v vl input voltage range v vl vl (overdriven) 4.75 5.25 v out output voltage (max1762, 1.8v fixed) v out v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = gnd, continuous conduction mode 1.773 1.8 1.827 v out output voltage (max1762, 2.5v fixed) v out v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = vl, continuous conduction mode 2.463 2.5 2.538 v out output voltage (MAX1791, 3.3v fixed) v out v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = gnd, continuous conduction mode 3.250 3.3 3.350 v out output voltage (MAX1791, 5v fixed) v out v vp = 7v to 20v, v vl = 4.75v to 5.25v, fb = vl, continuous conduction mode 4.925 5 5.075 v out output voltage (adj mode) v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = out, continuous conduction mode 1.231 1.250 1.269 v output voltage adjust range 0.5 5.5 v out input resistance adjustable-output mode 300 800 1700 k ? fb input bias current v fb = 1.3v -0.1 0.1 a soft-start ramp time zero to full i lim 1700 s v out = 1.25v, v vp = 6v 666 740 814 on-time (note 2) t on v out = 5v, v vp = 6v 2550 2830 3110 ns minimum off-time (note 2) t off 300 400 500 ns vl quiescent supply current fb = gnd, v vl = 5v, out forced above the regulation point 153 260 a v vl = float 227 410 vp quiescent supply current fb = gnd, out forced above the regulation point, v vp = 20v v vl = 5v 93 200 a vl shutdown supply current v vl = 5v, shdn = gnd 2 15 a vp shutdown supply current s hd n = gn d , m easur ed at v p , v v l = 0 or 5v 4 12 a vl output voltage i load = 0 to 25ma, v vp = 5v to 20v 4.5 4.65 4.75 v stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks _______________________________________________________________________________________ 3 electrical characteristics (continued) (v vp = 15v, vl enabled, c vl = 1f, c ref = 0.1f, t a = 0 to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units reference voltage v vl = 4.75v to 5.25v, no load 1.98 2 2.02 v reference load regulation i ref = 0 to 50a 0.01 v ref sink current ref in regulation 10 a ref fault lockout voltage falling edge 1.6 v output undervoltage threshold (foldback) with respect to regulation point, no load 60 70 80 % output undervoltage lockout time (foldback) from shdn signal going high v out < 0.6 x regulation point 10 20 42 ms current limit threshold v ilim -90 -100 -110 mv thermal shutdown threshold hysteresis = 10 o c 160 o c vl undervoltage lockout threshold rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v dh gate driver on-resistance v vp = 6v to 20v, measure at 50ma 5 8 ? dl gate driver on-resistance (pullup) dl, high state, measure at 50ma 5 8 ? dl gate driver on-resistance (pulldown) dl, low state, measure at 50ma 1 5 ? dh gate driver source/sink current v dh = 3v, v vp = 6v 0.6 a dl gate driver sink current v dl = 2.5v 0.9 a dl gate driver source current v dl = 2.5v 0.5 a shdn logic input high threshold voltage v ih 1.6 v shdn logic input low threshold voltage v il 0.6 v max1762 v out = 1.8v fixed MAX1791 v out = 3.3v fixed 50 100 150 mv max1762 v out = 2.5v fixed dual mode threshold voltage MAX1791 v out = 5v fixed 2.5 3.25 4 v shdn logic input current shdn = 0 or 5v -2 2 a
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 4 _______________________________________________________________________________________ electrical characteristics (v vp = 15v, vl enabled, c vl = 1f, c ref = 0.1f, t a = -40 to +85 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units vp input voltage range v vp 520v vl input voltage range v vl vl (overdriven) 4.75 5.25 v out output voltage (max1762, 1.8v fixed) v out v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = gnd, continuous conduction mode 1.773 1.827 v out output voltage (max1762, 2.5v fixed) v out v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = vl, continuous conduction mode 2.463 2.538 v out output voltage (MAX1791, 3.3v fixed) v out v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = gnd, continuous conduction mode 3.250 3.350 v out output voltage (MAX1791, 5v fixed) v out v vp = 7v to 20v, v vl = 4.75v to 5.25v, fb = vl, continuous conduction mode 4.925 5.075 v out output voltage (adj mode) v vp = 5v to 20v, v vl = 4.75v to 5.25v, fb = out, continuous conduction mode 1.231 1.269 v fb input bias current v fb = 1.3v -0.2 0.2 a v out = 1.25v, v vp = 6v 666 814 on-time (note 2) t on v out = 5v, v vp = 6v 2550 3110 ns minimum off-time (note 2) t off 250 550 ns vl quiescent supply current fb = gnd, v vl = 5v, out forced above the regulation point 260 a v v l = float 410 vp quiescent supply current fb = gnd, out forced above the regulation point v vp = 20v v v l = 5v 200 a vl shutdown supply current v vl = 5v, shdn = gnd 15 a vp shutdown supply current s hd n = gn d , m easur ed at v p , v v l = 0 or 5v 12 a vl output voltage i load = 0 to 25ma, v vp = 5v to 20v 4.5 4.75 v reference voltage v vl = 4.75v to 5.25v, no load 1.98 2.02 v reference load regulation i ref = 0 to 50a 0.01 v ref sink current ref in regulation 10 a output undervoltage threshold (foldback) with respect to regulation point, no load 60 80 % output undervoltage lockout time (foldback) from shdn signal going high, v out < 0.6 x regulation point 10 42 ms current-limit threshold v ilim -90 -110 mv
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks _______________________________________________________________________________________ 5 note 1: specifications to -40 c are guaranteed by design, not production tested. note 2: one-shot times are measured at the dh pin (vp = 15v, c dh = 400pf, 90% point to 90% point; see drawing below for measurement details). electrical characteristics (continued) (v vp = 15v, vl enabled, c vl = 1f, c ref = 0.1f, t a = -40 to +85 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units vl undervoltage lockout threshold rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v shdn logic input high threshold voltage v ih 1.6 v shdn logic input low threshold voltage v il 0.6 v max1762 v out = 1.8v fixed MAX1791 v out = 3.3v fixed 50 150 mv max1762 v out = 2.5v fixed dual mode threshold voltage MAX1791 v out = 5v fixed 2.5 4 v dh 90% 90% t on
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 6 _______________________________________________________________________________________ typical operating characteristics (t a = +25 c, unless otherwise noted.) 100 0 0.1 1 10 100 1000 10,000 max1762 efficiency vs. load (2.5v) 20 max1762/91 toc01 load current (ma) efficiency (%) 40 60 80 10 30 50 70 90 v vp = 5v v vp = 12v v vp = 7v v vp = 18v 100 0 0.1 1 10 100 1000 10,000 MAX1791 efficiency vs. load (3.3v) 20 max1762/91 toc05 load current (ma) efficiency (%) 40 60 80 10 30 50 70 90 v vp = 18v v vp = 12v v vp = 7v v vp = 5v 100 0 0.1 1 10 100 1000 10,000 MAX1791 efficiency vs. load (3.0v) 20 max1762/91 toc06 load current (ma) efficiency (%) 40 60 80 10 30 50 70 90 v vp = 7v v vp = 18v v vp = 12v v vp = 5v -0.6 -0.4 -0.5 -0.2 -0.3 0 -0.1 0.1 010 5 152025 vl voltage error vs. output current max1762/91 toc08 vl current (ma) vl voltage error (%) v vp = 12v v out = 2.5v 100 0 0.1 1 10 100 1000 10,000 MAX1791 efficiency vs. load (5v) 20 max1762/91 toc04 load current (ma) efficiency (%) 40 60 80 10 30 50 70 90 v vp = 7v v vp = 18v v vp = 12v 250 275 325 300 350 375 frequency vs. supply voltage max1762/91 toc07 supply voltage (v) frequency (khz) 511 81417 v out = 3.3v v out = 5.0v v out = 2.5v v out = 1.8v load = 1a 100 0 0.1 1 10 100 1000 10,000 max1762 efficiency vs. load (1.8v) 20 max1762/91 toc02 load current (ma) efficiency (%) 40 60 80 10 30 50 70 90 v vp = 18v v vp = 12v v vp = 5v v vp = 7v 100 0 0.1 1 10 100 1000 10,000 max1762 efficiency vs. load (1v) 20 max1762/91 toc03 load current (ma) efficiency (%) 40 60 80 10 30 50 70 90 v vp = 7v v vp = 12v v vp = 5v v vp = 18v
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks _______________________________________________________________________________________ 7 typical operating characteristics (continued) (t a = +25 c, unless otherwise noted.) load-transient response max1762/91 toc12 v out ac-coupled 100mv/div i l 2a/div 100 s/div v vp = 12v, i l = 0 to 2a, v out = 2.5v load-transient response max1762/91 toc13 v out ac-coupled 100mv/div i load 2a/div 100 s/div v vp = 12v, i load = 0 to 2a, v out = 1.8v line-transient response max1762/91 toc11 vp 1v/div 7v v out ac-coupled 20mv/div 100 s/div v vp = 7.5v to 8v, i load = 0, v out = 2.5v shutdown and startup waveforms (i l = 300ma) max1762/91 toc15 v out 2v/div i lx 1a/div shdn 5v/div 2ms/div v vp = 8v, i load = 300ma, v out = 2.5v shutdown and startup waveforms (i l = 2.5a) max1762/91 toc16 i lx 2a/div shdn 5v/div v out 2v/div 2ms/div v vp = 8v, i load = 2.5a, v out = 2.5v output overload waveforms max1762/91 toc14 100 s/div v vp = 12v, i load = 0 to 3a, v out = 2.5v v out ac-coupled i load 2a/div 4.0 4.6 4.4 4.2 4.8 5.0 5.2 5.4 5.6 5.8 6.0 511 81417 supply current vs. input voltage (shutdown) max1762/91 toc10 vp (v) supply current (a) no load 0 100 50 200 150 250 300 511 81417 supply current vs. input voltage max1762/91 toc09 vp (v) supply current ( a) v out = 3.3v no load
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 8 _______________________________________________________________________________________ standard application circuit the standard application circuit (figure 1) generates a low-voltage output for general-purpose use in notebook computers (i/o supply, fixed cpu, core supply, and dram supply). this dc-dc converter steps down bat- tery voltage from 5v to 20v with high efficiency and accuracy to a fixed voltage of 1.8v/2.5v/adj (max1762) or 3.3v/5.0v/adj (MAX1791). both the max1762 and MAX1791 can be configured for adjustable output volt- ages (v out > 1.25v), using a resistive voltage-divider from v out to fb to adjust the output voltage (figure 2). similarly, figure 3 shows an application circuit for v out < 1.25v, where a resistive voltage-divider from ref to fb is used to set the output voltage. figure 4 shows how to set the regulator s current limit with an external sense resistor from cs to gnd. table 1 lists the com- ponents for each application circuit, and table 2 con- tains contact information for the component manufacturers. detailed description the max1762/MAX1791 step-down controllers are tar- geted at low-voltage chipsets and ram power supplies for notebook and subnotebook computers, with addi- tional applications in digital cameras, pdas, and handy-terminals. maxim s proprietary quick-pwm pulse-width modulator (figure 5) is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency (300khz) over a wide range of input voltages (5v to 20v). the max1762 has fixed 1.8v or 2.5v outputs, while the MAX1791 has fixed 3.3v or 5.0v output voltages. using an external resistive divider, v out can be set between 0.5v and 5.5v on either device. quick-pwm architec- ture circumvents the poor load-transient response of fixed-frequency current-mode pwms. this type of design avoids the problems commonly encountered with conventional constant-on-time and constant-off- time pwm schemes. pin name function 1vl +4.65v linear regulator output. serves as the supply input for the dl gate driver and supplies up to 25ma to external loads. vl can be overdriven using an external 5v supply. bypass vl to gnd with at least a 1 f ceramic capacitor. 2 ref 2v reference voltage output. bypass to gnd with 0.1 f ceramic capacitor. ref can deliver up to 50 a for external loads. 3fb feedback input. connect to an external resistive divider from out to gnd in adjustable version. regulates to 1.25v. fb also serves as dual mode select pin. connect fb to gnd for a fixed 1.8v ( m ax 1762) or 3.3v (m ax 1791) outp ut, or to vl for a fi xed 2.5v (m ax 1762) or 5.0v ( m ax 1791) outp ut. 4 out output voltage connection. out is used for sensing the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. 5 shdn shutdown input. connect to a voltage less than v il (<0.6v) to shut down the device. connect to a voltage greater than v ih (>1.6v) for normal operation. 6 gnd analog and power ground 7 dl low-side gate driver output. dl swings between vl and gnd. 8cs current-sense connection. for lossless current sensing, connect cs to the junction of the mosfets and inductor. for more accurate current sensing, connect cs to a current-sense resistor from the source of the low-side switch to gnd. 9 dh high-side gate driver output. dh swings between vp and gnd. 10 vp battery voltage supply input. used for pwm one-shot timing and as the input for the vl regulator and dh gate drivers. pin description
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks _______________________________________________________________________________________ 9 figure 1. typical application circuit for fixed voltage fb q1 l1 7 h q2 c2 1 f c3 0.1 f gnd c1 10 f cs dh c4 220 f vp dl out ref shdn v vp v out vl max1762 MAX1791 10 ? 1 f figure 2. typical application circuit for adjustable output v out > 1.25v fb q1 r1 r2 l1 7 h q2 c2 1 f c3 0.1 f gnd c1 10 f cs dh c4 220 f vp dl out ref shdn v vp v out vl max1762 MAX1791 10 ? 1 f figure 3. typical application circuit for v out < 1.25v fb q1 r1 r2 l1 7 h q2 c2 1 f c3 0.1 f gnd c1 10 f cs dh c4 220 f vp dl out ref shdn v vp v out vl max1762 MAX1791 10 ? 1 f
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 10 ______________________________________________________________________________________ figure 4. operation with external current-sense resistor fb q1 r s l1 10 h q2 c2 1 f c3 0.1 f gnd c1 10 f cs dh c4 150 f vp dl out ref shdn v vp v out vl max1762 MAX1791 10 ? 1 f table 1. component selection for standard applications component 1.8v/2.5v/3.3v/5.0v at 2a 1v at 2a input voltage range 5v to 20v 5v to 20v inductor (h) 7 5.2 l1 inductor cdrh104-7r0nc sumida cdrh104-5r2nc sumida q1 mosfets nds8958a fairchild si4539ady fairchild c1 input capacitor tmk432bj106km taiyo yuden tmk432bj106 taiyo yuden c2 vl cap emk3160j105kl taiyo yuden lmk316bj475 taiyo yuden c3 ref cap umk316bi104kh taiyo yuden umk316bi104kh taiyo yuden c4 output cap 10tpb220m sanyo 6tpb150m sanyo
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks ______________________________________________________________________________________ 11 vp input and vl logic supply an internal linear regulator supplied by vp produces the +4.65v supply (vl) that powers the pwm controller, logic, reference, and other blocks within the max1762/MAX1791. this +4.65v low-dropout linear regulator can supply up to 25ma for external loads. bypass vl to gnd with at least a 1f ceramic capaci- tor. v vp can range between 5v and 20v. vl is turned off when the device is in shutdown and drops by approximately 500mv during a fault condition, such as when the output is short circuited to ground, and recov- ers when shdn is cycled or power is reset. if vl is not driven externally, then v vp should be at least 5v to ensure operation. if v vp is running from a 5v (10%) supply, v vp should be externally connected to vl. table 2. component manufacturers manufacturer usa phone website info coiltronics 561-241-7876 www.coiltronics.com fairchild semiconductor 408-822-2181 www.fairchildsemi.com sanyo 619-661-6835 www.secc.co.jp usa 847-956-0666 sumida japan 81-3-3607-5111 www.sumida.com taiyo yuden 408-573-4150 www.t-yuden.com figure 5. functional block diagram q1 q2 out gnd dh dh driver c out vp dl dl driver ton 1-shot trig q on-time compute on/off control 2v v ref timer c vl c in vos -100mv cs ilim linear reg feedback mux (figure 9) 1-shot t on t off trig vl c ref ref ref out fb ref -30% fb vl out v in vp vp out vp uvp latch s r q q q s r q max1762 MAX1791 shdn 10 ? 1 f
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 12 ______________________________________________________________________________________ overdriving the vl regulator with an external 5v supply also increases the max1762/MAX1791s efficiency. the max1762/MAX1791 include an input undervoltage lockout (uvlo) circuit that prevents the device from switching until vl > 4.4v (max). uvlo ensures there is a sufficient drive for the external mosfets, prevents the high-side mosfet from being turned on for near 100% duty cycle, and keeps the output in regulation. voltage reference (ref) the 2v reference (ref) is accurate to 1% over tem- perature, making ref useful as a precision system ref- erence. bypass ref to gnd with a 0.1f (min) ceramic capacitor. ref can supply up to 50a for external loads. however, if tight-accuracy specs for either v out or ref are essential, avoid loading ref. loading slight- ly reduces the main output voltage by an amount that tracks the reference-voltage load regulation error. free-running constant on-time pwm controller with input feed-forward the pwm control architecture is a quasi-fixed-frequen- cy constant on-time current-mode type with voltage feed-forward. this architecture relies on the output rip- ple voltage to provide the pwm ramp signal; thus, the output filter capacitor s esr acts as a feedback resis- tor. the control algorithm is very simple. the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. there is another one-shot that sets a minimum amount of off- time (500ns max). the on-time one-shot triggers when all of the following conditions are met: the error com- parator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. on-time one-shot the on-time of the one-shot is inversely proportional to the battery voltage as measured by the vp input, and directly proportional to the output voltage sensed at out: where k is internally fixed at 3.349s, and 0.075v is a factor that accounts for the expected drop across the synchronous switch. this arrangement maintains a switching frequency that is nearly constant as v batt , i load , and v out are changed. table 3 shows the oper- ating frequency range for the max1762/MAX1791. note that the output voltage adjust range for continu- ous-conduction operation is restricted by the non- adjustable 0.5s (max) minimum off-time. worst-case dropout performance is determined by the minimum on-time spec. the worst-case duty factor limit is: with v batt = 6v and v out = 5v. therefore, with ir volt- age drops in the loop included, the minimum input volt- age to achieve v out = 5v is about 6.1v, using the step-down transfer function equation for duty cycle (dc = v out /v in ). typical units exhibit better performance. note that transient response is somewhat degraded near dropout, and the circuit may need additional bulk output capacitance to support fast load changes. automatic pulse-skipping switchover this pwm control algorithm automatically switches over to pulse-skipping operation at light loads. the max1762/MAX1791 truncates the low-side switch s on- time when the inductor current drops to zero. the load current level at which pulse-skipping/pwm crossover occurs is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 6). the inductor current is never allowed to go negative. if the output voltage is above its regulation point and the inductor current reaches zero, the low-side driver is switched off. once the output voltage falls below its regulation point, the high-side driver is switched on. this causes a dead time in between when the high- side and low-side drivers are on, skipping pulses and resulting in the switching frequency slowing at light loads, thereby improving efficiency. mosfet gate drivers the dh and dl drivers are optimized for driving moder- ate-size power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment where a large v batt - v out differential exists. the high- side driver (dh) is rated for 0.6a source/sink capability and swings from vp to gnd. the low-side driver (dl) is i kv 2l v-v load(skip) out vp out vp = ? ? ? ? ? ? v t tt on min on min off max () () ( ) = ? = + 2.55 s 2.55 s+0.5 s 84% t v +0.075v v on out batt = () k table 3. operating frequency device k ( s) min (khz) typ (khz) max (khz) max1762/MAX1791 3.349 268.7 298.5 328
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks ______________________________________________________________________________________ 13 rated for +0.5a, -0.9a source/sink capability and swings from vl to gnd. the internal pulldown transistor that drives dl low is robust, with a 1 ? typical on-resistance. this helps pre- vent dl from being pulled up during the fast rise time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfet. however, for high-current applications, some combinations of high-and low-side fets may cause excessive gate-drain coupling, which can lead to poor efficiency, emi, and shoot-through currents. an adaptive dead-time circuit monitors the dl output and prevents the high-side fet from turning on until dl is fully turned off. the dead time at the other edge (dh turning off) is determined by a fixed 35ns (typ) internal delay. low-side current-limit sensing (ilim) the current-limit circuit employs a unique valley cur- rent-sensing algorithm that uses the on-state resistance of the low-side mosfet as a current-sensing element. if the current-sense signal is below the current-limit threshold (-100mv from cs to gnd), the pwm is not allowed to initiate a new cycle (figure 7). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the mosfet on-resistance, inductor value, and battery voltage. if greater current-limit accuracy is desired, cs must be connected to the junction of the low-side switch source and a current-sense resistor to gnd. the current limit will be 0.1v/r sense , and the accuracy will be 10%. a resistive voltage-divider from the inductor s switching mode to ground can be used to adjust the current-limit sense voltage that appears at cs (figure 8). keep the impedance at this mode low to avoid errors at cs. por and soft-start power-on reset (por) occurs when v batt rises above approximately 2v, resetting the fault latch and soft-start counter and preparing the pwm for operation. uvlo circuitry inhibits switching until v vp rises above 4.1v, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. the ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%; 100% current is available after approximately 1.7ms. output undervoltage protection the output uvlo function is similar to foldback current limiting but employs a timer rather than a variable cur- rent limit. the output undervoltage protection is enabled 20ms after por or when coming out of shut- down. if the output is under 70% of the nominal value, figure 6. pulse-skipping/discontinuous crossover point inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out ? i ? t = figure 7. ?alley?current-limit threshold point inductor current i limit i load 0 time i peak figure 8. using a resistive voltage-divider to adjust current- limit sense voltage to 200mv cs dh dl v p max1762 MAX1791 1.0k ? v out 1.0k ?
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 14 ______________________________________________________________________________________ then the pwm is latched off and will not restart until vp power is cycled, or shdn is toggled low then high. design procedure begin by establishing the input voltage range and max- imum load current before choosing an inductor and its associated ripple-current ratio (lir). the following four factors dictate the rest of the design: 1) input voltage range. the maximum value (v vp (max) ) must accommodate the maximum ac adapter voltage. the minimum value (v vp(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. 2) maximum load current. there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stress and fil- tering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stress and thus drives the selection of input capaci- tors, mosfets, and other critical heat-contributing components. modern notebook cpus generally exhibit, i load = i load(max) x 0.8. 3) switching frequency. the max1762/MAX1791 have a nominal switching frequency of 300khz. 4) inductor ripple-current ratio (lir). lir is the ratio of the peak-to-peak ripple current to the average inductor current. size and efficiency trade-offs must be considered when setting the inductor ripple-cur- rent ratio. low inductor values cause large ripple currents, resulting in the smallest size but poor effi- ciency and high output noise. the minimum practi- cal inductor value is one that causes the circuit to operate at critical conduction (where the inductor current just touches zero with every cycle). inductor values lower than this grant no further size-reduc- tion benefit. the max1762/MAX1791s pulse-skipping algorithm ini- tiates skip mode at the critical conduction point. so, the inductor operating point also determines the load-cur- rent value at which switchover occurs. the optimum point is usually found between 20% and 50% ripple current. the inductor ripple current also impacts transient- response performance, especially at low v vp - v out difference. low inductor values allow the inductor cur- rent to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the peak amplitude of the output transient (v sag ) is also a function of the maximum duty factor, which can be cal- culated from the on-time and minimum off-time: where minimum off-time = 0.5s (max). inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as fol- lows: example: i load(max) = 2a, v vp = 7v, v out = 1.6v, f = 300khz, 35% ripple current or lir = 0.35: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice. the core must be large enough not to saturate at the peak inductor current (i peak ): i peak = i load(max) + [(lir/2) ? i load(max) ] determining current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: i valley > i load(max) - [(lir/2) ? i load(max) ] where i valley = minimum current-limit threshold volt- age divided by the r ds(on) of q2. for the max1762/ MAX1791, the minimum current-limit threshold is 90mv. use the worst-case maximum value for r ds(on) from the mosfet q2 data sheet, and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each c of temperature rise. l khz a h = = 1.6v(7v -1.6v) 7 300 0 35 2 59 . . l = ? v(v-v) v lir i out vp out vp load(max) v )l v v +t v-v v -t sag load(max) out vp off(min) out out vp out vp off(min) 2 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ( ? ik cvk 2
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks ______________________________________________________________________________________ 15 examining the 2a circuit example with a maximum r ds(on) = 52m ? at +85 c temperature reveals the fol- lowing: i valley = 90mv / 52m ? = 1.73a checking the corresponding i load(max) reveals: a current-sense resistor can be connected from cs to gnd to set the current limit for the device. the max1762/MAX1791 will use the sense resistor instead of the r ds(on) of q2 to limit the current. the maximum value of the sense resistor can be calculated with the equation: i limit = 90mv / r sense output capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core convert- ers and other applications where the output is subject to large load transients, the output capacitor s size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: where v dip is the maximum tolerable transient voltage drop. in non-cpu applications, the output capacitor s size depends on how much esr is needed to maintain an acceptable level of output voltage ripple: where vp-p is the peak-to-peak output voltage ripple. the actual microfarad capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and volt- age rating rather than by capacitance value (this is true of tantalum, sp, pos, and other electrolytic-type capacitors). when using low-capacity filter capacitors such as ceramics, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag equation in the design procedure section). the amount of overshoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. stability considerations stability is determined by the value of the esr zero (f esr ) relative to the switching frequency (f). the point of instability is given by the following equation: where: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capaci- tors in widespread use at the time of publication have typical esr zero frequencies of 20khz. in the design example used for inductor selection, the esr needed to support a specified ripple voltage is found by the equation: where lir is the inductor ripple current ratio, and i load is the average dc load. using a lir = 0.35 and an average load current of 2a, the esr needed to support 50mvp-p ripple is 71m ? . do not use high-value ceramic capacitors directly across the fast feedback inputs (fb to gnd) without taking precautions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it s easy to add enough series resistance by placing the capaci- tors a couple of inches downstream from the junction of the inductor and fb pin. unstable operation manifests itself in two related but dis- tinctly different ways: double-pulsing and fast-feedback loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there isn t enough voltage ramp in the output voltage signal. this r v lir esr ripple(p-p) load = i ? esr esr out 1 2 rc ? ? esr ? v li cv peak 2 out 2 r vp - p lir i esr load(max) r v i esr dip load(max) i 1 - 0.5 lir 1.73a 1 - 0.5 0.35 2.1a load(max) valley == = i
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 16 ______________________________________________________________________________________ fools the error comparator into triggering a new cycle immediately after the 500ns minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can cause the output voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the max1762/MAX1791 ev kit manual) and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. don t allow more than one cycle of ringing after the initial step-response under- or overshoot. input capacitor selection the input capacitor must meet the ripple-current require- ment (i rms ) imposed by the switching currents. nontantalum chemistries (ceramic or os-con ) are pre- ferred due to their resilience to power-up surge currents: power mosfet selection dc bias and output power considerations dominate the selection of the power mosfets used with the max1762/MAX1791. take care not to exceed the device s maximum voltage ratings. in general, both switches are exposed to the supply voltage, so select mosfets with v ds (max) greater than vp (max). gate drives to the n-channel and p-channel mosfets are not symmetrical. the n-channel device is driven from ground to the logic supply vl, while the p-channel device is driven from vp to ground. the maximum rat- ing for v gs for the n-channel device is usually not an issue; however, v gs (max) for the p-channel must be at least vp (max). since v gs (max) is usually lower than v ds (max), gate drive constraints often dictate the required p-channel breakdown rating. for moderate input-to-output differentials, the high-side mosfet (q1) can be sized smaller than the low-side mosfet (q2) without compromising efficiency. the high-side switch operates at a very low duty cycle under these conditions, so most conduction losses occur in q2. for maximum efficiency, choose a high- side mosfet (q1) that has conduction losses (i 2 r x duty cycle) equal to the switching losses (cv vp 2 f). make sure that the conduction losses at the minimum input voltage do not exceed the package thermal limits or violate the overall thermal budget. conduction losses plus switching losses at the maximum input voltage should not exceed the package ratings or violate the overall thermal budget (see mosfet power dis- sipation ). in addition to efficiency considerations, the selection of the r ds(on) of the low-side mosfet must account for the regulator s required current limit. choose a mos- fet that has a low enough resistance over the operat- ing temperature range such that the device will not enter current limit during normal operation (see determining current limit ). conversely, ultra-low r ds(on) devices may set the current limit too high and may result in only incremental improvements in efficien- cy. some large n-channel fets also have substantial interelectrode capacitance. verify that the max1762/ MAX1791 dl driver can hold the gate off when the high side switch turns on. cross-conduction problems can occur when the high-side switch turns on due to cou- pling through the n-channel s parasitic drain-to-gate capacitance. the max1762/MAX1791 have adaptive dead-time cir- cuitry that prevents the high-side and low-side mosfets from conducting at the same time (see mos- fet gate drivers ). even with this protection, it is still possible for delays internal to the mosfet to prevent one mosfet from turning off while the other is turned on. the maximum mismatch time that can be tolerated is 60ns. select devices that have low turn-off times, and make sure that nfet(t d (off,max)) - pfet(t d (on,min)) < 60ns, and pfet(t d (off,max)) - nfet(t d (on,min)) < 60ns. failure to do so may result in efficiency-killing shoot- through currents. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet, the worst-case power dissipation (pd) due to resistance occurs at min- imum battery voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltage. however, the r ds(on) required to stay within package power-dis- sipation limits often limits how small the mosfet can be. again, the optimum occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. high- pd(q1 resistance) v v ir out vp(min) load ds(on) 2 = ? ? ? ? ? ? ? ? i v(v-v) rms load out vp out vp = ? ? ? ? ? ? ? ? i i os-con is a trademark of sanyo.
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks ______________________________________________________________________________________ 17 side switching losses don t usually become an issue until the input is greater than approximately 15v. switching losses in the high-side mosfet can become an insidious heat problem when maximum battery volt- age is applied, due to the squared term in the cv 2 f switching loss equation. if the high-side mosfet cho- sen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v vp(max) , reconsider your choice of high-side mos- fet. calculating the power dissipation in q1 due to switch- ing losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn- off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source induc- tance, and pc board layout characteristics. the follow- ing switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on q1: where c rss is the reverse transfer capacitance of q1, and i gate is the peak gate-drive source/sink current. for the low-side mosfet, the worst-case power dissi- pation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, the circuit must be overde- signed to tolerate: i load = i limit(high) + (lir / 2 ) ? i load(max) where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. this means that the mosfet must be very well heatsinked. if short-cir- cuit protection without overload protection is enough, a normal i load value can be used for calculating compo- nent stresses. during the period when the high-side switch is off, cur- rent circulates from ground to the junction of both fets and the inductor. as a consequence, the polarity of the switching node is negative with respect to ground. if unchanged, this voltage will be approximately 0.7v (a diode drop) at both transition edges while both switch- es are off. in between the edges, the low-side switch conducts; the drop is i l ? r ds(on) . if a schottky clamp is connected across the low-side switch, the initial and final voltage drops will be reduced, improving efficien- cy slightly. choose a schottky diode (d1) having a forward voltage low enough to prevent the q2 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional and can be removed if efficiency isn t critical. applications issues dropout performance the output voltage adjust range for continuous-conduc- tion operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. when working with low input voltages, the duty-factor limit must be calcu- lated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the t on k-factor. also, keep in mind that transient response performance of buck regulators operating close to dropout is poor, and bulk output capacitance must often be added. dropout design example: v in = 7v (min), v out = 5v, f = 300khz. the required duty cycle is : the worst-case on-time is: the maximum ic duty factor based on timing con- straints of the max1762/max1792 is: which meets the required duty cycle. remember to include inductor resistance and mosfet on-state volt- age drops (v sw ) when doing worst-case dropout duty- factor calculations. fixed output voltages the max1762/MAX1791 dual mode operation allows the selection of common voltages without requiring external components (figure 9). connect fb to gnd for duty t t+t on(min) on(min) off(max) == + = 218 218 05 082 . .. . ? s ss t v + 0.075 v 5v + 0.075 7v on(min) out vp == = k ss 335 90 218 .%. ? dc v+v v-v 5v + 0.1v 7v - 0.1v req out sw vp sw === 074 . pd(q2) - v v ir out vp(max) load ds 2 = ? ? ? ? ? ? ? ? 1 pd (q1 switching) cv i i rss vp(max) load gate 2 = ? ? ? ? ? ? ? ? ?
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks 18 ______________________________________________________________________________________ a fixed +1.8v (max1762) or 3.3v (MAX1791) output. connect fb to vl for a fixed 2.5v (max1762) or 5.0v (MAX1791) output. otherwise, connect fb to a resistive voltage-divider for an adjustable output. setting the output voltage select v out > 1.25v for the max1762/MAX1791 by connecting fb to a resistive voltage-divider between v out and gnd (figure 2). choose r2 to be about 10k ? , and solve for r1 using the equation: where v fb = 1.25v. for a v out = 3.0v, r2 = 10k ? and r1 = 14k ? . for a desired v out < 1.25v, connect fb to a resistive voltage-divider between ref and out (figure 3). choose r1 to be about 50k ? , and solve for r2 using the equation: where v fb = 1.25v and v ref = 2.0v. for a v out = 1.0v, r1 = 50k ? and r2 = 16.5k ? . under these condi- tions, a minimum load of v ref - v fb / r1 >15a is required. pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. this is especially true when multiple converters are on the same pc board where one circuit can affect the other. the switching power stages require particular attention (figure 10). refer to the MAX1791 ev kit manual for a specific layout example. if possible, mount all of the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pc board layout: isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. use a separate gnd plane under out. avoid the introduction of ac cur- rents into the gnd ground planes. run the power plane ground currents on the top side only, if possi- ble. keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. inductor and gnd connections to the synchronous rectifiers for current limiting must be made using kelvin sensed connections to guarantee the cur- rent-limit accuracy. with so-8 mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while connect- ing gnd and cs inside (underneath) the max package. when trade-offs in trace lengths must be made, it s preferable to allow the inductor charging path to be made longer than the discharge path. for example, it s better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ensure that the out connection to c out is short and direct. however, in some cases it may be desir- able to deliberately introduce some trace length between the out connector node and the output filter capacitor (see stability considerations ). route high-speed switching nodes (cs, dh, and dl) away from sensitive analog areas (fb). use gnd as an emi shield to keep radiated switching noise away from the ic s feedback divider and ana- log bypass capacitors. r2 v-v v-v r1 out fb fb ref = ? ? ? ? ? ? vv r1 r2 out fb =+ ? ? ? ? ? ? 1 figure 9. feedback mux max1762 to error amp 0.150v 2.5v fb fixed 1.8v fixed 3.3v out
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks ______________________________________________________________________________________ 19 layout procedure 1) place the power components first, with ground ter- minals adjacent (q1 source, c in , c out ). if possi- ble, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the synchro- nous-rectifier mosfets, preferably on the back side in order to keep cs, gnd, and the dl gate drive lines short and wide. the dl gate trace must be short and wide (measuring 50mils to 100mils wide if the mosfet is 1in from the controller ic). 3) place the v l bypass capacitor near the controller ic. 4) make the dc-dc controller ground connections as follows: near the ic, create a small analog ground plane. connect this plane to gnd, and use this plane for the ground connection for the ref and v vp bypass capacitors and fb dividers. 5) on the board s top side (power planes), make a star ground to minimize crosstalk between the two sides. the top-side star ground is a star connection of the input capacitors, side 1 low-side mosfet. keep the resistance low between the star ground and the source of the low-side mosfets for accu- rate current limit. connect the top-side star ground (used for mosfet, input, and output capacitors) to the small island with a single short, wide connection (preferably just a via). 6) connect the output power planes directly to the out- put filter capacitor positive and negative terminals with multiple vias. chip information transistor count: 3520 process: s8e1fp figure 10. pc board layout example agnd pgnd use agnd plane to: - bypass v cc and ref - terminate external fb divider (if used) - pin-strap control inputs use pgnd plane to: - bypass v vp - connect pgnd to the topside star ground via to ground note: example shown is for dual n-channel mosfet. connect pgnd to agnd beneath the max1762/MAX1791 at one point only as shown. gnd p1 n1 vout vl vbatt l1 c2 c1 d1
max1762/MAX1791 high-efficiency, 10-pin max, step-down controllers for notebooks maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information 10lumax.eps

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